Request Information for PCIe Connectivity Subsystems

PCIe Connectivity

Linux PCIe Stream Framework for Xilinx

PCIe as a hardware/software interface when combined with AXI4-Streaming suggests using a Streaming Dataflow architecture. This is also known as  Producer / Consumer or FIFO-In / FIFO-Out and uses so-called Blocking Reads and Blocking Writes for interfaces. Because AXI4-Streaming implements back-pressure / flow-control, a Blocking Read waits until there is data to be received, and a Blocking Write waits with sending more data in case FIFOs are full.

Our PCIe Stream Framework for Xilinx FPGAs is a complete hardware/software subsystem comprising Linux device drivers (open source) and Xilinx PCIe function blocks, all delivered as a reference design (Xilinx Vivado project including all necessary TCL scripts, instantiating Xilinx catalogue IP, tested / synthesized on Xilinx Vivado Version 2017.4 and targeted to the Xilinx VCU118 Devkit).

Our Linux PCIe Stream Framework supports the Xilinx PCIe hard-IP for Xilinx 7-series family, or newer.