Request Information for Network Protocol Accelerator Platform

TCP/UDP/IP Network Protocol Accelerator

 

The German Fraunhofer Heinrich-Hertz-Institute (HHI) partners with MLE to market the proven TCP/IP & UDP Network Protocol Acceleration Platform (NPAP).  This customizable solution enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for multiple links at 1Gbit/s, 10Gbit/s, and beyond. 

MLE is a licensee of Fraunhofer HHI, and offers a range of technology services, sublicenses and business models compatible with customer's ASIC or FPGA project settings, world-wide.

Core Benefits

  • Bring full TCP/UDP/IP connectivity to FPGAs even if no CPU available (“Full Acceleration”).
  • Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”).
  • Complete and customizable turn-key solutions and IP cores based on the TCP/UDP/IP stack from the Fraunhofer HHI.
  • All MAC / Ethernet / IPv4 / UDP / TCP processing is implemented in HDL code, synthesizable to modern FPGAs.
  • User applications can either be implemented in FPGA logic or in software via application-specific interfaces to CPUs.

Applications

  • Hardware-only implementation of TCP/IP in FPGA
  • Networked storage, such as iSCSI
  • Test & Measurement connectivity
  • Video-over-IP for 3G and 6G transports
  • Increase line rates in 10GbE.
  • Reduce latency in point-to-point communication.
     

Key Features

  • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
  • Parameterizable for 8-bit (1GigE) or 128-bit (10GigE, 40GigE) data width
  • Multiple, parallel TCP engines for scalable processing
  • Network Interface Card functionality with Bypass (optional)
  • Point-to-point or LAN capable
  • Full line rate of TPRmax = 9.5896 Gbps
  • TCP R/W latency of TTR(W) ≥ 1.4 µs
  • UDP R/W latency of TUR(W) ≥ 0.75 µs
  • Round trip time  of RTTmin ≥ 2.25 µs

Remote Evaluation System

Try out the Network Protocol Accelerator Platform using MLE's Remote Evaluation System which lets you connect to MLE's IP core evaluation lab via a remote connection so you can evaluate and try out this IP core from MLE and partners.

  • Evaluate and try the IP core when it is running live on an FPGA system under your control - which saves you from engineering time to integrate and compile the IP core on target hardware
  • Have your own copy of a virtual environment - which allows you to run your tests, keep your logs, for example, if your calendar forces you to interrupt your current evaluation

This remote evaluation is based on the NPAP-10G Evaluation Reference Design (ERD) for Xilinx Zynq UltraScale+ MPSoC running on the ZCU102 DevKit. The ZCU102 Devkit is physically connect via a 10GigE Twinax cable to a Mellanox ConnectX-4 LX 10G/25G NIC which sits inside the host running Your VM.

Zynq Ultrascale+ MPSoC Evaluation System

  • Targeted to Xilinx Zynq Ultrascale+ MPSoC ZU9 (see Eval Guide)
  • Quad-Core ARM A53MP runs Xilinx PetaLinux
  • Netperf and TCP-/UDP-Loopback example instances
    (click block diagram above for more details)
  • SFP+ for 10GigE via Twinax or Fibre
  • Supports Vivado design flow with High-Level Synthesis design option
  • 10 GigE Resource Count (128-bit )
    • Vivado 2017.3 targeting XCZU9EG
    • Full stack (UDP and 2 TCP engines) ~30k LUTs
    • For each additional TCP engine ~10k LUTs
  • Runs on Xilinx on ZCU102 Development Kit

Availability

 NPAP (as IP core or reference design) is available for the following FPGA families:

Products Availability Matrix

 

Datasheets and Documentation

Download the NPAP-10G/25G Product Brochure for Xilinx FPGA Devices.

Download the NPAP-100G Product Brochure for Xilinx Alveo Cards.

Read the NPAP Datasheet describing FPGA resources and TCP / UDP / IP functionalities implemented.

Please refer to these Technical Documents to learn more about Network Protocol Acceleration:

 

Pricing

NPAP is available as a combination of Intellectual Property (IP) Cores, reference designs, and design integration services:

  Deliverables Example Pricing

Network Processing Device

Integrated processing device solution, built on top of leading FPGA technology, encapsulating one or more Network Protocol Accelerators for 1GbE and/or 10GbE.

Based on NRE and unit volume

Intellectual Property (IP) Cores

Single-Project or Multi-Project Use; ASIC or FPGA; Modular and application-specific IP cores, and example design projects; delivered as encrypted netlists or RTL.

starting at $78,000.-

Evaluation Reference Design (ERD) Available upon request as FPGA design project, with optional customizations (different target device, different transceivers, etc) free-of-charge or $1,480.- per engineering day

Application-specific R&D Services

Advanced network protocol acceleration R&D services with access to acceleration experts from Fraunhofer HHI and/or MLE.

$1,480.- per engineering day
 

Please contact MLE for additional details on NPAP products and services or other product and licensing options.

 

Frequently Asked Questions

How compatible is NPAP with other NICs?

NPAP is integrated with the FPGA vendors PCS/PMA layer and thus is compatible with other IEEE compliant Ethernet Network Interface Cards (NIC) for 1 GigE, 10 GigE, 25 GigE, 40 GigE, 50 GigE, 100 GigE. Please refer to the FPGA device vendors documentation of the subsystem for further information.
 

How compatible is NPAP with other TCP/UDP/IP stacks?

NPAP implements all networking functions required by IETF RFC 1122 and thus is interoprable with software stacks from Microsoft Windows, Open-Source Linux (3.x or newer) as well as Mellanox/libvma or SolarFlare OpenOnload. Please refer to the NPAP Datasheet for more information.
 

Does NPAP use embedded Block-RAM (BRAM), and how much?

Yes, typically, we configure and instantiate NPAP with BRAMs for the Rx/Tx buffers. For applications where NPAP transmits data to a server we suggest 128K Bytes per TCP session (i.e. TCP port instance) to accomodate the (slower) processing of the software TCP stack running on the Recipient. Please refer to the NPAP Datasheet for more information.

What are typical TCP buffer sizes?

Here is the metric to determine TCP buffer sizes for NPAP (keep in mind, that TCP buffers are placed on both ends: Tx side and Rx side):

Buffer size (in bits) = Bandwidth (in bits-per-second) * RTT (in seconds)

RTT is the Round-Trip Time which is the time for the Sender to transmit the data plus the time-of-flight for the data, plus the time it takes the Recipient to check for packet correctness (CRC), plus the time for the Recipient to send out the ACK, plus the time-of-flight for the ACK, plus the time it takes the Sender to process the ACK and release the buffer.

For example:

  1. If the recipient is NPAP in a direct connection then we can assume ACK times less than 20 microseconds, i.e. buffer sizes shall be 200k bits. Means in this case a 32 kBytes on-chip BlockRAM per TCP session will be sufficient.
  2. If the recipient is software then RTT can be much longer, mostly due to the longer processing times in the OS on the recipient side. For a modern Linux we can assume RTT of 100 microseconds, or longer (see here [1] or run a 'ping localhost' on your machine). Means buffer sizes shall be around 1M bits, or the 128K Bytes of BRAM we typically instantiate.

 

end faq

 

Fraunhofer HHI

Founded in 1949, the German Fraunhofer-Gesellschaft undertakes applied research of direct utility to private and public enterprise and of wide benefit to society. With a workforce of over 23,000, the Fraunhofer-Gesellschaft is Europe’s biggest organization for applied research, and currently operates a total of 67 institutes and research units. The organization’s core task is to carry out research of practical utility in close cooperation with its customers from industry and the public sector.

Fraunhofer HHI was founded in 1928 as "Heinrich-Hertz-Institut für Schwingungsforschung“ and joined in 2003 the Fraunhofer-Gesellschaft as the "Fraunhofer Institute for Telecommunications, Heinrich-Hertz-Institut„. Today it is the leading research institute for networking and telecommunications technology, “Driving the Gigabit Society” .