Request Information for Network Protocol Accelerator Platform

TCP/UDP/IP Network Protocol Accelerator

 

The German Fraunhofer Heinrich-Hertz-Institute (HHI) partners with MLE to market the proven TCP/IP & UDP Network Protocol Acceleration Platform (NPAP).  This customizable solution enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for multiple links at 1Gbit/s, 10Gbit/s, and beyond. 

MLE is a licensee of Fraunhofer HHI, and offers a range of technology services, sublicenses and business models compatible with customer's ASIC or FPGA project settings, world-wide.

Core Benefits

  • Bring full TCP/UDP/IP connectivity to FPGAs even if no CPU available (“Full Acceleration”).
  • Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”).
  • Complete and customizable turn-key solutions and IP cores based on the TCP/UDP/IP stack from the Fraunhofer HHI.
  • All MAC / Ethernet / IPv4 / UDP / TCP processing is implemented in HDL code, synthesizable to modern FPGAs.
  • User applications can either be implemented in FPGA logic or in software via application-specific interfaces to CPUs.

Applications

  • Hardware-only implementation of TCP/IP in FPGA
  • Networked storage, such as iSCSI
  • Test & Measurement connectivity
  • Video-over-IP for 3G and 6G transports
  • Increase line rates in 10GbE.
  • Reduce latency in point-to-point communication.
     

Key Features

  • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
  • Parameterizable for 8-bit (1GigE) or 128-bit (10GigE, 40GigE) data width
  • Multiple, parallel TCP engines for scalable processing
  • Network Interface Card functionality with Bypass (optional)
  • Point-to-point or LAN capable
  • Full line rate of TPRmax = 9.5896 Gbps
  • TCP R/W latency of TTR(W) ≥ 1.4 µs
  • UDP R/W latency of TUR(W) ≥ 0.75 µs
  • Round trip time  of RTTmin ≥ 2.25 µs

Fidus Sidewinder-100 Evaluation System

  • Targeted to Xilinx Zynq Ultrascale+ MPSoC ZU19EG (see Eval Guide)
  • Quad-Core ARM A53MP runs Xilinx PetaLinux
  • Netperf and TCP-/UDP-Loopback example instances
    (click block diagram above for more details)
  • QSFP28 for 1/10/25 GigE via Twinax or Fibre
  • Supports Vivado design flow with High-Level Synthesis design option
  • 25 GigE Resource Count (128-bit )
    • Vivado 2017.3 targeting XCZU19EG
    • Full stack (UDP and 2 TCP engines) ~30k LUTs
    • For each additional TCP engine ~10k LUTs
  • Runs on on Sidewinder ZU19EG Storage Accelerator PCIe Card from Fidus Systems

Zynq Ultrascale+ MPSoC Evaluation System

  • Targeted to Xilinx Zynq Ultrascale+ MPSoC ZU9 (see Eval Guide)
  • Quad-Core ARM A53MP runs Xilinx PetaLinux
  • Netperf and TCP-/UDP-Loopback example instances
    (click block diagram above for more details)
  • SFP+ for 10GigE via Twinax or Fibre
  • Supports Vivado design flow with High-Level Synthesis design option
  • 10 GigE Resource Count (128-bit )
    • Vivado 2017.3 targeting XCZU9EG
    • Full stack (UDP and 2 TCP engines) ~30k LUTs
    • For each additional TCP engine ~10k LUTs
  • Runs on Xilinx on ZCU102 Development Kit

Zynq-7045 Evaluation System

  • Targeted to Xilinx Zynq-7045 on ZC706
  • Dual-Core ARM A9MP runs Xilinx PetaLinux
  • Netperf and TCP-/UDP-Loopback example instances
    (click block diagram above for more details)
  • SFP+ for 10GigE via Twinax or Fibre
  • Supports Vivado design flow with High-Level Synthesis design option
  • 1 GigE Resource Count (8-bit )
    • Vivado 2014.4 targeting XC7Z045
    • Full stack (UDP and 2 TCP engines) ~13k LUTs
    • For each additional TCP engine ~5k LUTs
  • 10 GigE Resource Count (128-bit )
    • Vivado 2014.4 targeting XC7Z045
    • Full stack (UDP and 2 TCP engines) ~30k LUTs
    • For each additional TCP engine ~10k LUTs
  • Runs on Xilinx ZC706 Development Kit

Availability

 NPAP (as IP core or reference design) is available for the following FPGA families:

Click here to check the availability for your target device

 

Datasheets and Documentation

Download the Network Protocol Accelerator Product Brochure.

Read the customer presentation TCP/UDP/IP Solutions for FPGAs.

Please refer to these Technical Documents to learn more about Network Protocol Acceleration:

 

Pricing

NPAP is available as a combination of Intellectual Property (IP) Cores, reference designs, and design integration services:

  Deliverables Example Pricing

Network Processing Device

Integrated processing device solution, built on top of leading FPGA technology, encapsulating one or more Network Protocol Accelerators for 1GbE and/or 10GbE.

Based on NRE and unit volume

10GbE Accelerated NIC

Network Interface Card with 10GbE, PCIe, single- or dual-FPGA, pre-programmed with NPAP configuration; also available as a complete reference design. 9,800.00 € (min. order quantity of 5)

Intellectual Property (IP) Cores

Single-Project or Multi-Project Use; ASIC or FPGA; Modular and application-specific IP cores, and example design projects; delivered as encrypted netlists or RTL.

starting at 78,000.00 €

Application-specific R&D Services

Advanced network protocol acceleration R&D services with access to acceleration experts from Fraunhofer HHI and/or MLE.

1,820.00 € per engineering day
 

Please contact MLE for additional details on NPAP products and services.

 

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