Request Information for Network Protocol Accelerator Platform

TCP/UDP/IP Network Protocol Accelerator

 

The German Fraunhofer Heinrich-Hertz-Institute (HHI) partners with MLE to market the proven TCP/IP & UDP Network Protocol Acceleration Platform (NPAP).  This customizable solution enables high-bandwidth, low-latency communication solutions for FPGA- and ASIC-based systems for multiple links at 1Gbit/s, 10Gbit/s, and beyond. 

MLE is a licensee of Fraunhofer HHI, and offers a range of technology services, sublicenses and business models compatible with customer's ASIC or FPGA project settings, world-wide.

Core Benefits

  • Bring full TCP/UDP/IP connectivity to FPGAs even if no CPU available (“Full Acceleration”).
  • Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”).
  • Complete and customizable turn-key solutions and IP cores based on the TCP/UDP/IP stack from the Fraunhofer HHI.
  • All MAC / Ethernet / IPv4 / UDP / TCP processing is implemented in HDL code, synthesizable to modern FPGAs.
  • User applications can either be implemented in FPGA logic or in software via application-specific interfaces to CPUs.

Applications

  • Hardware-only implementation of TCP/IP in FPGA
  • Networked storage, such as iSCSI
  • Test & Measurement connectivity
  • Video-over-IP for 3G and 6G transports
  • Increase line rates in 10GbE.
  • Reduce latency in point-to-point communication.

Key Features

  • Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
  • Parameterizable for 8-bit (1GigE) or 128-bit (10GigE, 40GigE) data width
  • Multiple, parallel TCP engines for scalable processing
  • Network Interface Card functionality with Bypass (optional)
  • Point-to-point or LAN capable
  • Full line rate of TPRmax = 9.5896 Gbps
  • TCP R/W latency of TTR(W) ≥ 1.4 µs
  • UDP R/W latency of TUR(W) ≥ 0.75 µs
  • Round trip time  of RTTmin ≥ 2.25 µs

Zynq-7045 Evaluation System

  • Targeted to Xilinx Zynq-7045 on ZC706
  • Dual-Core ARM A9MP runs Xilinx PetaLinux
  • Netperf and TCP-/UDP-Loopback example instances
    (click block diagram for more details)
  • SFP+ for 10GigE via Twinax or Fibre
  • Supports Vivado design flow with High-Level Synthesis design option
  • 1 GigE Resource Count (8-bit )
    • Vivado 2014.4 targeting XC7Z045
    • Full stack (UDP and 2 TCP engines) ~13k LUTs
    • For each additional TCP engine ~5k LUTs
  • 10 GigE Resource Count (128-bit )
    • Vivado 2014.4 targeting XC7Z045
    • Full stack (UDP and 2 TCP engines) ~30k LUTs
    • For each additional TCP engine ~10k LUTs

Pricing

NPAP is available as a combination of Intellectual Property (IP) Cores, reference designs, and design integration services:

  Deliverables Example Pricing

Network Processing Device

Integrated processing device solution, built on top of leading FPGA technology, encapsulating one or more Network Protocol Accelerators for 1GbE and/or 10GbE.

Based on NRE and unit volume

10GbE Accelerated NIC

Network Interface Card with 10GbE, PCIe, single- or dual-FPGA, pre-programmed with NPAP configuration; also available as a complete reference design. 9,800.00 € (min. order quantity of 5)

Intellectual Property (IP) Cores

Single-Project or Multi-Project Use; ASIC or FPGA; Modular and application-specific IP cores, and example design projects; delivered as encrypted netlists or RTL.

starting at 78,000.00 €

Application-specific R&D Services

Advanced network protocol acceleration R&D services with access to acceleration experts from Fraunhofer HHI and/or MLE.

1,820.00 € per engineering day
 

Please contact MLE for additional details on NPAP products and services.

 

Availability

NPAP is available for the following FPGA families:

Available for: Stratix V, Arria 10, Stratix 10.

Available for: Virtex-6, Kintex-7, Virtex-7, Kintex Ultrascale, Virtex-Ultrascale.

Available for: Zynq-7000 as IP core or reference design.

Please contact MLE if you are interested in support for other FPGA devices.

 

Datasheets and Documentation

Download the Network Protocol Accelerator Product Brochure.

Read the customer presentation TCP/UDP/IP Solutions for FPGAs.

Please refer to these Technical Documents to learn more about Network Protocol Acceleration:

 

Fraunhofer HHI

Founded in 1949, the German Fraunhofer-Gesellschaft undertakes applied research of direct utility to private and public enterprise and of wide benefit to society. With a workforce of over 23,000, the Fraunhofer-Gesellschaft is Europe’s biggest organization for applied research, and currently operates a total of 67 institutes and research units. The organization’s core task is to carry out research of practical utility in close cooperation with its customers from industry and the public sector.

Fraunhofer HHI was founded in 1928 as "Heinrich-Hertz-Institut für Schwingungsforschung“ and joined in 2003 the Fraunhofer-Gesellschaft as the "Fraunhofer Institute for Telecommunications, Heinrich-Hertz-Institut„. Today it is the leading research institute for networking and telecommunications technology, “Driving the Gigabit Society” .