Company - Missing Link Electronics

MLE Participates at Lattice Developers Conference 2024

December 10, 2024Lattice, Network Acceleration, PLC, Robo/TSN, SmartNIC, Time-Sensitive Networking (TSN), Virtualize Industrial Network, Virtualizing PLC, vPLC

The Lattice Developers Conference 2024 takes place both virtually and physically in San Jose, CA, on December 10, 2024. Here, MLE presents the Robo/TSN for Industrial Network Virtualization with Multi-Gigabit Ethernet and Multi Protocols.

MLE Robo/TSN is an advanced FPGA-based network virtualization technology designed for multi-Gigabit TSN (Time Sensitive Networking), leveraging open standards to deliver seamless, high-speed connectivity. It integrates access points and SmartNICs to efficiently connect high-speed devices such as sensors, robotic arms, and machinery to datacenter, supporting data transfer rates of up to 100Gbps. Robo/TSN can also virtualize PLCs and run PLC system on datacenter infrastructure with advantages like virtualization, containerization, redundancy, backup organization etc. and without any compromises concerning real-time and high-speed requirements.

Features of MLE Robo/TSN:

Bridging/ Tunneling of several protocols like PCIe, Ethercat, Profinet, Ethernet, CAN, etc.
Scalable from 1 to 100 Gbps
Precision time synchronization with IEEE TSN or IEEE 1588 v2 (CERN White Rabbit)
Hardware accelerated deterministic transport with Ultra Low Latency (RTT < 600 ns)
Reliable transports via TCP/IP and/or Quad-RP/IP
Optional security features MACsec, IPSec, TLS

Learn more about the performance of MLE Robo/TSN solution with Lattice FPGAs at Lattice Developers Conference 2024!

Join Conference Online

Learn more about Robo/TSN

MLE Participates at AMD/Xilinx Security Working Group 2024

December 5, 2024AMD/Xilinx, Network Acceleration, NPAP, RTL, Security, TCP/IP, TLS, Versal Gen 2, ZYNQ Ultrascale+

MLE Participates AMDXilinx Security Working Group 2024

The AMD-Xilinx Security Working Group takes place face-to-face in Munich, Germany, from December 10-11, 2024. Presentations include the latest security features in Versal Gen 2 and other AMD FPGA families, and updates for the product roadmap.

MLE, a Premier AMD Alliance Member, will participate and showcase its latest security solutions and services. These include TCP/IP with TLS (NPAP and TLS) implemented in RTL for high-speed, secure communication, as well as expertise in hardening AMD Versal and AMD Zynq UltraScale+ MPSoC-based systems for use in data center networking, automotive and telecommunications.

MLE Upstreamed an Implementation for VCXO-less White Rabbit nodes on an AMD Zynq UltraScale+ MPSoC ZCU102 Evaluation Board

October 21, 2024AMD ZC706, AMD ZCU102, FPGA, Mixed-Mode Clock Managers, MMCMs, QPLL, Quad Phase-Locked-Loops, VCOX, White Rabbit

MLE is actively contributing to the White Rabbit Project, a group focusing on advancing network synchronization research, to synchronize their beamforming and detector units to achieve the goal of sub-nanosecond synchronization.

White Rabbit delivers sub-nanosecond accuracy in synchronizing networked devices over distances of tens of kilometers. Typically, implementing this technology in FPGAs requires external voltage-controlled crystal oscillators (VCXOs) for measurement and adjustment. However, such components are often missing on commercially off-the-shelf (COTS) development boards. This forces interested developers to invest inexpensive, specialized hardware just to get started with White Rabbit technology.

MLE has overcome this challenge by developing a VCXO-less White Rabbit solution that operates entirely using FPGA resources. This breakthrough enables the deployment of White Rabbit nodes across a range of development boards without the need for external components.

▲ MLE implements VCXO-less White Rabbit solution on AMD Zynq UltraScale+ MPSoC ZCU102 Evaluation Board (WR Switch loaned by DESY)

Now the VCXO-less White Rabbit solution has been upstreamed to the public White Rabbit repository. MLE’s implementation is based on the widespread and affordable AMD Zynq UltraScale+ MPSoC ZCU102 Evaluation Board. The released source code consists of two merge requests covering both firmware and gateware. Both are designed for broad reusability to simplify and accelerate White Rabbit implementations on other FPGA platforms, such as the AMD Zynq 7000 SoC ZC706 Evaluation board, which is a current work-in-progress at MLE, as well as the AMD Zynq UltraScale+ RFSoC ZCU111 Evaluation Board.

Currently, the VCXO-less White Rabbit solution is under review and testing by members of the White Rabbit Collaboration at CERN.

MLE Joins the Standardization Group for Embedded Technologies (SGeT) for Harmonized FPGA Module Standard Development

September 5, 2024FPGA SoM, trenz

Standardization Group for Embedded Technologies (SGeT) is dedicated to developing, promoting, and marketing open standards for embedded hardware and software, and, recently, has embraced working on the needs for FPGA systems. MLE joins its Harmonized FPGA Module (HFM) Standard Development Team to contribute to the standardization of FPGA and FPGA SoC System-on-Modules, with the goal of lowering the barriers to FPGA adoption and development.

In collaboration with its partner, Trenz Electronics—also a SGeT member—MLE has been accelerating FPGA development by utilizing Trenz’s FPGA SoMs that are pre-integrated with MLE’s IP cores. The establishment of a uniform standard for FPGA and FPGA SoC System-on-Modules will further speed up the transition from prototyping to final design, significantly reducing time to market for FPGA development projects.

MLE Releases NPAP TCP/UDP/IP Stack Version 2.4.1

August 26, 2024IP Update, Network Acceleration, NPAP, TCP/IP

MLE has released Version 2.4.1 of its Network Protocol Accelerator Platform (NPAP).

NPAP is the TCP/UDP/IP Full Accelerator from Fraunhofer HHI which enjoys production use in FPGA applications for automotive, industrial, medical, robotics, test & measurement and wired/wireless communications.

Changes include optimizations and fixes mostly for TCP interoperability with other TCP implementations such as Windows 10 Enterprise LTSC.

Please refer to the updated datasheet MLE TB20240819 or visit http://MLEcorp.com/NPAP for more information.

SNIA Storage Developers Conference, Sept. 16-18, 2024 in Santa Clara, CA

August 13, 2024Homa, Network Acceleration, SmartNIC, TCP/IP

The Storage Developers Conference (SDC) 2024 of SNIA, the Storage and Networking Industry Alliance, will be held Sept. 16-18 in Santa Clara, CA. There, MLE will present “Complementing TCP with Homa, Stanford’s Reliable, Rapid Request-Response Protocol“.

At SDC 2023 last year, we presented Homa, a new datacenter protocol invented by John Ousterhout at Stanford University. Overall, Homa provides significant advantages over TCP when it comes to tail latency and infrastructure efficiency in real-life networks, but not compatible with TCP API. We were told to come back with answers regarding Homa:

A) Can Homa and TCP co-exist in the same network peacefully?

B) How can Homa be accelerated to become more useful and applicable for networked storage?

In our presentation this year we will provide those answers and new collaboration results.

First, we will show network simulation analysis for traffic comprising Homa and TCP. Because of TCP’s congestion management, both protocols not only can co-exist but also be complemented in order to get the best from both: TCP for data streams plus Homa for (shorter) messages with improved tail-end latencies.

We then look into John’s open source implementation for the Linux Kernel, HomaModule and how this can be combined with another open source project, FPGA NIC Corundum.io, for FPGA acceleration of the Homa protocol.

We present experimental results by applying known concepts of CPU offloading to Homa, especially receive side scaling (RSS), segmentation and large receive offloading. After applying the offloads to a traffic pattern with significant traffic portion of payload chunks, the MTU (maximum transmission unit), both the slowdown and RTT, decreases by 5x. The outcome is a Reliable, Rapid, Request-Response Protocol with benefits in storage networking and potential use for networking GPU clusters.

Date: Monday September 16th, 2024

Session: Storage Networking (starts at 10:35pm PST)

Location: Room Winchester, Hyatt Regency Santa Clara, Santa Clara, CA

MLE Awarded AMD 2023 Premier Adaptive Computing Partner of the Year

June 28, 2024Alveo, AMD, High Speed Data Recording

MLE wins AMD 2023 Premier Adaptive Computing Partner — AMD’s Donna Best (left) and Rhett Whatcott (right) awarded MLE’s Bob Baker (middle) the AMD 2023 Premier Adaptive Computing Partner of the Year award.

San Jose, CA, June 2024 – At the AMD Premier Partner and ATP Summit 2024 held in San Jose this June, Missing Link Electronics (MLE) was honored with the Premier Adaptive Computing Partner of the Year award for the EMEA region. This recognition highlights MLE’s outstanding contributions and unwavering commitment to advancing AMD FPGA technology across various industries and applications.

Since becoming a member of the AMD Partner Program in 2011, MLE has played an essential role in driving the adoption and integration of AMD’s cutting-edge FPGA technology. MLE has leveraged its expertise to promote AMD’s Alveo technology, particularly the Alveo U55 and Alveo V80, through its involvement in key customer engagements for data recording for high-speed cameras.

MLE wins AMD Premier Adaptive Computing Partner Award 2023

MLE’s deep understanding of FPGA computing has allowed it to position AMD’s Alveo technology as a cornerstone for high-performance applications. The company’s strategic initiatives and technical acumen have made Alveo technology more accessible and attractive to more customers, thereby enhancing its adoption and integration into various sophisticated systems.

AMD recognizes MLE’s current contributions to the Alveo U55 and V80 as a catalyst for future engagements, broadening the customer base and enhancing the technology’s growth potential.

In their nomination statement, AMD highlighted:

Missing Link Electronics’ dedication to promoting innovative technologies across various applications continues to be vital, and their valuable contributions to the field make them deserving of recognition and this award.

This accolade from AMD not only acknowledges MLE’s past achievements but also underscores the potential for future collaborations and innovations. As the demand for high speed networking and storage grows, MLE is well-positioned to continue its leadership in the field, driving further advancements and expanding the reach of AMD’s technology.

MLE’s commitment to excellence is reflected in its ongoing projects and future plans. We are constantly exploring new FPGA technologies to ensure users to efficiently adopt AMD FPGAs. Our ability to adapt and meet changing market needs has made it a valued partner of AMD and a key player in the technology space.

Berlin 6G Conference 2024

June 28, 20246G, Precision Time Protocol (PTP), White Rabbit

Berlin 6G Conference is the annual networking event of the German 6G Program, organized by the 6G Platform Germany, will take place at the Berlin Congress Center (BCC) from July 2-4, 2024.

The 6G Platform Germany is an R&D initiative with a total funding of €700 million. One of the core topics is the combination of a secure radio and sensing, so-called Integrated Communication and Sensing (ICAS) with aims to develop such a combination for communication and sensing of the environment and to integrate it into a joint system for the future mobile radio standard 6G.

MLE has been actively contributing to the 6G-ICAS4Mobility project in respect of high-accuracy networking technology with precision time synchronization.

MLE Presents “FPGA Based 400GBit/s Data Recorder – Insight into Different Pitfalls and Design Choices” at FPGA Conference 2024

June 18, 2024BRAM, High Bandwidth Memory (HBM2), High Speed Data Recording, NVMe SSD, PCI Express, Storage Acceleration

FPGA Conference EW24 Banner - 400Gbit FPGA Data Recording IP

The FPGA Conference Europe 2024 will be held July 2-4 in Munich, Germany. There, MLE will present “FPGA Based 400GBit/s Data Recorder – Insight into Different Pitfalls and Design Choices.”

Modern Systems can combine a lot of sensors like cameras, radars, Lidar or high speed ADC/DAC. During development, it is often required to record raw data. A FPGA Based High Speed Recorder can collect data from many different sources and can record them on non-volatile memory. Building a High Speed Data Recorder has many pitfalls which can cause the project to fail as a single flaw can have a heavy impact on performance.

This presentation will walk through our lessons learned from building such a recorder: starting by analyzing the data path, discussing the impact of data granularity and data width, different local buffer options such as DDR / HBM2 / UltraRAM / BRAM, characteristics of AXI4 / PCIe and also the limitations of most NVMe SSDs in the aspect of sustained writing performance. Then the presentation will end with an architectural overview of the final system and the achieved performance.

Date: Tuesday July 2th, 2024

Track 1 – Application (starts at 4:30pm CEST)

Location: Hotel NH München Ost Conference Center, Munich, Germany

Join us at FPGA Conference 2024 to learn more details about the high-speed 400GBit/s data recording technology!