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    Contact MLE for IP-Cores
    Please fill in the form below, so we can send you the relevant information regarding the IP-Cores of interest.


      Low-Latency 10G/25G Ethernet MACNPAP TCP/UDP/IP StackNVMe Streamer Gen3NVMe Streamer Gen4Key-Value StoreLinux PCIe FrameworkPCIe Long-Range TunnelPCIe NTBIBM OpenCAPISoft ADCSoft DACXilinx USB 2.0 EHCIXilinx XAUIXilinx RXAUIZynq Storage Exension

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      Encryted Network Accelerator Solutions

      FPGA TCP/UPD/IP - Network Protocol Accelerator Platform (NPAP)

      Encrypted Network

      Accelerator Solutions (ENAS)

      Encrypted Network Acceleration Solutions (ENAS) with High-level Security

      TCP-TLS 1.3 for Secure 10/25/50 GigE

      Encrypted Network Accelerator Solutions (ENAS) are joint solutions of TCP/IP and TLS (also named as TCP-TLS 1.3 IP core) to ensure secure and reliable connection between devices over LAN and WAN. It implements Transport Layer Security (TLS), a cryptographic protocol that provides end-to-end data security, on top of the Transmission Control Protocol (TCP) layer.

      ENAS is designed with hardware-based high-level security and enables high-bandwidth, low-latency communication for FPGA-based systems. The TCP-TLS 1.3 IP core can accelerate the device network up to 10/25/50G Ethernet line rates with data being protected through high-speed, hardware-based encryption and decryption under TLS 1.3. All the cryptographic mathematical operations are performed entirely in the FPGA, and the keys are stored in dedicated internal FPGA memory.

      Since the TCP/IP stack and the TLS 1.3 security protocol – including importantly both key exchange and key management – are both executed entirely in hardware, the joint solution has both scalable high-speed performance and minimise attack surface, especially when compared to a software-based approach. The FPGA hereby utilises the hardware Root of Trust, best suited for applications like critical communication in defence, space technology, and energy production and distribution .

      Encrypted Network Acceleration Solution - NPAP Block Diagram with TLS

      Core Benefits

      • Resource-optimised IP core available for FPGAs and ASIC designs
      • High-speed traffic encryption and decryption
      • Secure design – Isolated processing and key management
      • All communication layers pre-designed for effective and fast integration

      Key Features

      • Highly modular TCP/UDP/IP stack with line rate up to 70Gbps in FPGA
      • Compact TLS 1.3 implementation
      • Hardware-based key management for IEC 62443 SL 3
      • Encrypted throughput of 10/25/50 Gbps
      • 128-bit bi-directional data paths with streaming interfaces
      • Multiple, parallel TCP engines for scalable processing

      Secure Communications for Applications Like

      • FPGA-based SmartNICs
      • In-Network Compute Acceleration (INCA)
      • Networked storage, such as iSCSI
      • Test & Measurement connectivity
      • Automotive backbone connectivity
      • System-of-Systems communication
      • Mission-critical environments

      Resource Utilization Estimation for 10GbE

      AMD/Xilinx Zynq Ultrascale+ LUT FFs RAMB 36 RAMBI 8 DSP 48
      NPAP ( Including MAC, ETH, IPv4, UDP, 3x TCP)* 33,500 35,000 71 10 6
      TLS1.3 (Including Crypto Engine, Key storage and
      handling)*
      43,000 28,000 25 18 4
      Total 76,500 63,000 96 28 4

      Pricing

      MLE’s Encrypted Network Accelerator Solutions (ENAS) is available as a combination of Intellectual Property (IP) Cores, reference designs, and design integration services:

      Product Name Deliverables Example Pricing
      Network Processing Device Integrated processing device solution, built on top of leading FPGA technology, encapsulating one or more Encrypted Network Accelerators for 10GbE, 25GbE and/or 50GbE.

      Based on NRE and unit volume 

      Inquire

      Intellectual Property (IP) Cores Single-Project or Multi-Project Use; ASIC or FPGA; Modular and application-specific IP cores, and example design projects; delivered as encrypted netlists or RTL. Inquire
      Evaluation Reference Design (ERD) Available upon request as FPGA design project, with optional customizations (different target device, different transceivers, etc) free-of-charge
      Application-specific R&D Services Advanced network protocol acceleration R&D services with access to acceleration experts from MLE and/or Xiphera. $1,680.- per engineering day 

      Documentation

      Xiphera Ltd.

      Xiphera

      Xiphera, Ltd, is a Finnish company designing hardware-based security solutions using standardised cryptographic algorithms. We have strong cryptographic expertise, extensive experience in system design, and deep knowledge on reprogrammable logic, enabling us to protect our customers’ critical information and assets.

      Xiphera’s product portfolio consists of secure and efficient cryptographic Intellectual Property (IP) cores, designed directly for Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs). Our widely applicable solutions for various end markets offer our customers peace of mind in a dangerous world.

      SATA Storage Extension for ZYNQ 7000

      ZYNQ SATA Connectivity

      SATA Storage Extension for ZYNQ 7000™

      Pre-validated ZYNQ SATA Solutions

      Since 2010, MLE has been providing SATA connectivity solutions for FPGAs. In 2014, as a result of close collaboration with Xilinx and Asics World Services, a new concept was introduced: To deliver a complete reference design with pre-integrated IP cores plus drivers and application software to reduce NRE costs and risks, and to shrink time-to-market for embedded applications.

      This, eventually, became the preferred option to connect SATA Harddisk Drives (HDD) and Solid-State Drives (SSD) to the Xilinx Zynq-7000 All Programmable SoC.

      MLE releases this SATA technology to support Xilinx Vivado version 2016.4, Xilinx PetaLinux version 2016.4 with a new Linux kernel 4.6 device API, plus streamlined product offerings to reflect the growing needs of embedded applications.

      MLE’s mature Zynq SATA Storage Extension (Zynq SSE) has been integrated into many successful customer projects. Zynq SSE responds to the embedded market’s needs for a simple, affordable solution to make use of modern SSDs. Zynq SSE is a fully integrated and pre-validated subsystem stack comprising 3rd-party SATA Host Controller and DMA IP cores from ASICS World Services, a storage micro-architecture from MLE, Xilinx PetaLinux, and an Open Source SATA Host Controller Linux kernel driver, also from MLE. Zynq SSE utilizes the Xilinx GTX Multi-Gigabit Transceivers to integrate physical SATA connectivity.

      Key Features of ZYNQ SATA Storage Extension (SSE)

      • Provides one single SATA host port for HDD or SSD connectivity
      • Compatible with SATA I (1.5 Gbps), SATA II (3 Gbps) and SATA III (6 Gbps) speeds
      • Access via a standard Linux block device interface and Linux filesystems
      • Fully integrated and tested SATA Host Controller IP Core
      • Fully integrated and tested DMA Controller IP Core
      • SATA driver for Linux/Petalinux available in binary and open source
      • Less than 3% resource utilization on a Zynq 7045 leaves more than 95% of Zynq resources for you
      ZYNQ SATA Connectivity - Block Diagram

      Core Benefits 

      • Reduce PCB footprint and BoM costs with this integrated FPGA solution
      • Reduce development cost, time and risks with this integrated, pre-validated system stack
      • Enables tight storage algorithm integration and test for de-duplification, scrubbing, compression, etc.

      Applications

      • Cost efficient, fast and reliable storage solutions for Embedded Systems
      • Supervisory, Control and Data Acquisition (SCADA) systems
      • Smart Storage, Software-defined Storage, Network-Attached Storage (NAS)
      • Storage and Retrieval for Test & Measurement
      • Video Imaging Record and Replay

      Pricing

      MLE’s license fee structure reflects the needs of Zynq’s Embedded Linux users for simple and affordable SATA with optional upgrade paths.

      Product Name Deliverables Pricing

      Evaluation Reference Design

      (Zynq SSE ERD)

      Binary-only system stack. Zynq PS / Linux software-only SATA API.

      Tried and tested to work on the Avnet Zynq Mini-ITX Boards 7Z045 and 7Z100 only.

      Evaluation-only license.

      free of charge

      Production Reference Design – Experts Edition

      (Zynq SSE PRD-EE)

      Complete, downloadable SATA-I/II/III system stack and Vivado 2016.4 design project with encrypted RTL code. Zynq PS / Linux software-only SATA API. (Same as Zynq SSE ERD)

      Production-ready: Pre-integrated and tested to be portable to Your target system hardware.

      Fully paid-up for, royalty-free, world-wide, Single-Project-Use License, synthesizable for 1 year.

      Bug-fixes only with basic support via email.

      $9,800.-

      Production Reference Design – Professional Edition

      (Zynq SSE PRD-PE)

      Complete, downloadable SATA-I/II/III system stack and Vivado 2016.4 design project with encrypted RTL code. Zynq PS / Linux software-only SATA API. (Same as Zynq SSE ERD)

      Production-ready: Pre-integrated and tested to be portable to Your target system hardware.

      Fully paid-up for, royalty-free, world-wide, Single-Project-Use License, synthesizable for 1 year.

      Up to 40 hours of premium support and integration design services via email, phone or online collaboration.

      $14,800.-

      Other SATA-I/II/III Offerings

      Multiple SATA host ports, PL-connected SATA host ports, Multi-Project-Use Licenses, RTL Source Code Licenses, other FPGA devices than Zynq, etc.

      Classical IP core licenses with annual maintenance, project-specific support and integration design service packages, etc.

      Starting at $19,800.-

      Inquire

      On the technical side, all Zynq SSE offerings implement one single SATA-I/II/III host operating the Xilinx GTX multi-gigabit transceivers at 1.5 or 3.0 or 6.0 Gbps and making use of modern SSDs Native Command Queueing (NCQ), Scatter-Gather Direct Memory Access (SG-DMA), Linux kernel drivers and Linux device tree. SATA API via a standard Linux block device from Linux user-space software.

      And yes, the license fee for the Production Reference Designs includes a fully paid-up for, royalty-free, world-wide, Single-Project-Use license for a single instance of the SATA Host Controller and DMA IP cores from ASICS World Services, the FPGA storage micro-architecture from MLE, and MLE’s SATA Host Controller Linux kernel driver.

      Documentation

      Frequently Asked Questions

      Zynq SSE is a turnkey solution and reference design which we intend as one single plug & play SATA host port add-on for Xilinx Zynq when running under Linux.

      While Zynq SSE instantiates IP cores, namely the full ASICS.WS SATA Host Controller and DMA Controller, it is not a soft FPGA IP Core by itself.

      Zynq SSE is closer to the other hard IP core I/O functions inside the Zynq Processing System (PS), like UART or SDIO: It is fully instantiated and ‘frozen’ and cannot be altered – other than you are able to change the pin assignment.

      Zynq SSE supports one (and only one) single SATA Host Port. If you need more, please contact us to discuss other possible solutions. There are several!

      Based on our experiences with Xilinx Zynq and SATA, a typical multi-host SATA system comes with certain performance requirements, which most often lean towards an application-specific architecture to deliver such performance.

      So, honestly, Zynq SSE cannot do that!

      However, we see a couple of options, depending on your project’s needs: For example, we can design for you a special multi-host reference design. Or, we can assist you in purchasing the ASICS.WS SATA Host Controller and DMA IP Core.

      Please contact us directly to discuss your options.

      ERD means Evaluation Reference Design. This is a complete compilable Vivado design project comprising an encrypted netlist of the MLE storage micro-architecture, plus all precompiled images, ready-to-run. ERD is a fully functional SATA host which runs for at least 12 hours, until it then times-out. You can request download instructions for an ERD from MLEcorp.com for testing, free-of-charge.

      PRD means Production Reference Design which comes in two forms, a PRD-3G for SATA-II and a PRD-6G for SATA-III with support for FPDMA and NCQ. PRD is a Vivado design project comprising an encrypted netlist of the MLE storage micro-architecture. A PRD must be purchased from MLEcorp.com which gives you the rights to take Zynq SSE into production for one single named project.

      The easiest way is to use the ERD for the Avnet mini-ITX Board which has a SATA header on board. The ERD comes with precompiled binaries. You can request a free-of-charge download from the Request Form on this page.

      Yes, please contact us and request download instructions for an ERD. ERD comes with a full Vivado design project for you to retarget to and test on your hardware. Please refer to the Zynq SSE Developers Guide of the ERD on how to re-compile. The Developers Guide will also provide information for the SATA capable reference clock to the GTX Clock input (150 MHz, low jitter).

      No, you will not need any License Key in order to run, or to re-compile, the Zynq SSE ERD.

      Yes, you will need two License Keys, a Compile-time License Key, and a Run-time License Key:

      • The Compile-time License Key is a Vivado Flex License Key file, tied to the host ID of your design workstation. With this key you can compile the Zynq SSE reference design to add your own design portions, change the SATA pin-out, and to generate bitfiles. We will send you one Compile-time License Key after proof-of-purchase.
      • The Run-time License Key is specific to your Zynq SSE and will disable the time-out mechanism. We will send you one Run-time License Key after proof-of-payment. Please follow the instructions in the MLE Zynq SSE Developers Guide to add this key file to the Linux root filesystem of your Zynq system.

      The Compile-time License Key will expire one year after the purchase date. This should be plenty to finish off your design project. The Run-time License Key will never expire.

      Each PRD contains everything you need to extend your Zynq system insert with one single SATA host port: This includes documentation – the so-called Developer’s Guide – and a Vivado design project with the ASICS.WS SATA Host Controller and DMA IP-Core inside the MLE microarchitecture and the Linux device drivers. Plus, all the (legal) rights to put those into production for your single, named project.

      You will receive all reasonable support, typically via Email.

      No. Once you purchase a PRD you will get the Compile-time Key and the Run-time Key to design-in and to operate a fully functional SATA host on Zynq. Our invoice together with the MLE Product License Agreement gives you the legal rights to make and use Zynq SSE for one single named project.

      Besides the online documentation listed on our website, as part of each ERD or PRD you will receive a complete developers guide which explains how to design-in Zynq SSE into your project.

      Without being legalistic here, the single-project-use license allows you use Zynq SSE within the same design project. If you need to fix errors within the FPGA design, or the PCB, and ship a new revision, that would be considered the same project. If you change the device package or re-design the PCB that would probably be another design project. We suggest to follow Xilinx’ concept for project based licensing.  Please do not hesitate to contact us if you need clarification.

      Without a purchased Run-time License Key, the SATA link in the PRD will disconnect after 12 hours. Once you have installed the Run-time License Key, this time-out will be disabled.

      No, the PRDs come with full functionality for SATA-II, or SATA-III, respectively.

      Yes, as long as you have a valid Compile-time License Key, you can upgrade from SATA-II to SATA-III. We will apply the payment for PRD-3G towards your payment of PRD-6G.

      The reason for pricing Zynq SSE is to reflect the needs of Zynq users who look for connectivity solutions, but not necessarily a full soft FPGA IP core as such:

      In general, the advantage of an IP core is that you can instantiate it freely in your design. You can parameterize and change and instantiate the IP core in many ways and as many times as needed. If you purchased the RTL source code version, you could even change the functionality. The drawback is the cost (and time) of integrating an IP core and the effort you have to put into driver development. And, sometimes, there is a support burdon for the IP core vendor, too.

      Zynq SSE is a turnkey reference design where the underlying IP core has been ‘frozen’. You can instantiate it exactly once (and only once) per device. By integrating this with Linux – including Linux device drivers – and making this available for Zynq-only we are able to come up with a great price for a Single-Project-Use license.

      We believe that this model has many advantages for all parties involved.

      No, Zynq SSE is technically and license-wise bundled with Zynq and Linux. However, we can support your project with a SATA IP core from ASICS.WS. Please read below and/or contact us.

      We have extensively tested Zynq SSE for Xilinx PetaLinux 2013.04. You can download this from the following git repository:

      https://github.com/Xilinx/linux-xlnx/branches

      In general, there is no reason why Zynq SSE should not work with other Linux Kernel versions applicable to Zynq.

      We took a conservative stand when we parameterized Zynq SSE. Key objective was to make it robust and work in almost all user cases. This limits the raw speed to approximately 200MB/sec for the PRD-3G. When we say ‘raw speed’ this is to and from the SATA Linux block device (a.k.a. /dev/sdX) without Linux filesystem layers involved. Obviously, filesystem handling adds to the processing burdon which leads to lower read/write speeds.

      If you need more performance than the raw speed to approximately 200MB/sec for the PRD-3, for example to max-out your super-fast SSD we believe we can help you. We are prepared to discuss with you acceleration options like bypassing the Linux system by writing directly into the SATA device, or other protocol acceleration techniques we have been working on. Just contact us directly!

      We would be more than happy to directly assist you in selecting and purchasing the right variant of a SATA IP Core from ASICS.WS. ASICS.WS has prepared us to discuss with you pricing and licensing options, or, for example, whether you should get HDL source code or just a netlist, or an evaluation, a single-project-use or a multi-project-use license.

      And, obviously, we do know the ASICS.WS SATA Host Controller and DMA IP Core in-and-out. So you can ask us technical questions, too!

      Sure, we have done turnkey solutions in the past and will be happy to discuss details with you, including PCB design and manufacturing.

      You can either download and compile the ERD for your target device and look at your Vivado utilization report. Or, below are the most important sections of the utilization report for a XC7Z100 device:

      Slice Logic        
      Site Type Used Loced Available Util%
      Slice LUTs 5922 0 277400 2.13
        LUT as Logic 5794 0 277400 2.08
        LUT as Memory 128 0 108200 0.11
          LUT as Distributed RAM 10 0    
          LUT as Shift Register 118 0    
      Slice Registers 4623 0 554800 0.83
        Register as Flip Flop 4623 0 554800 0.83
        Register as Latch 0 0 554800 0
      F7 Muxes 35 0 138700 0.02
      F8 Muxes 2 0 69350 <0.01
                   
      Memory        
      Site Type Used Loced Available Util%
      Block RAM Tile 3 0 755 0.39
        RAMB36/FIFO* 3 0 755 0.39
          FIFO18E1 only 1      
          RAMB36E1 only 2      
        RAMB18 1 0 1510 0.06
          RAMB18E1 only 1      
      * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
                   
      Clocking        
      Site Type   Used Loced Available Util%
      BUFGCTRL 8 0 32 25
      BUFIO 0 0 32 0
      MMCME2_ADV 2 0 8 25
      PLLE2_ADV 0 0 8 0
      BUFMRCE 0 0 16 0
      BUFHCE 0 0 168 0
      BUFR 0 0 32 0

      XPS USB 2.0 EHCI Host Controller

      XPS USB 2.0 EHCI Host Controller

      XPS USB 2.0 Host Controller IP Cores

      As of October 2011, Xilinx handed over to MLE sales and support for the Xilinx XPS USB 2.0 EHCI Host Controller. Available in Revision 2.00a, this IP Core allows users to connect FPGAs to full-speed and high-speed USB devices for human-machine interface applications, cameras and storage. The current release supports Spartan-3, Spartan-6 or Virtex-4, Virtex-5, Virtex-6 FPGAs in a Big-Endian PLB-based architecture. A Little-Endian AXI4-based architecture for 7-series FPGAs will be available soon for USB 2.0 Host Controller.

      USB 2.0 Host Controller - Block Diagram

      Core Benefits of USB 2.0 Host Controller

      • Reduce PCB footprint and BoM costs with this integrated FPGA solution
      • Reduce development cost, time and risks with this integrated, pre-validated system stack
      • Counter parts obsolescence
      • Supported by Linux and PetaLinux

      Applications

      Extend FPGA-based Embedded Systems with USB 2.0 connectivity to add Off-the-shelf components for:

      • Thumbdrive storage
      • HDD and SSD storage
      • Human Interface Devices (HID)
      • Bluetooth
      • WiFi 802.11abgn
      • GSM/UMTS/LTE

      Pricing

      MLE provides a three-phase product integration roadmap for customers:

      Product Name Deliverables Pricing

      Trial Version

      Integrated and delivered with Xilinx ISE. Fully functional with timeout after approx. 4 hours.

      free of charge

      Production License

      Single-Project or Multi-Project Use License; shipped as encrypted RTL code plus Xilinx ISE synthesis license key.

      starting at $20,000.-

      Support

      Support from Certified Xilinx engineers at MLE available on a T&M basis. Inquire

      Source code

      RTL Source Code for inspection purposes available under NDA. Inquire

      Documentation

      Mixed Signal FPGAs

      Mixed Signal FPGAs

      Mixed Signal FPGAs

      IP Cores for Mixed Signal FPGA Design

      MLE’s patent pending Mixed Signal FPGA solutions make Delta-Sigma-Modulator technology applicable to your next Embedded System project.

      When it comes to processing legacy data protocols FPGA offer very cost efficient alternatives to the – sometimes hard to get – original circuits. MLE’s Mixed-Signal FPGA technology further broadens the application space from pure digital protocols to so-called “amplitude-modulated” protocols which require plenty of configurable analog I/Os  embedded inside proven off-the-shelf FPGA devices.

      Standard Approach MLE Mixed Signal FPGAs
      • Discrete active components required to extend the FPGA with analog I/Os

      • Increased parts count and PCB footprint

      • Additional effort required to ensure simultaneous time-synchronous data processing

      Mixed Signal FPGAs - Standard Approach

      • No active peripheral components, analog I/Os are directly integrated into the FPGA

      • Reduced parts count and PCB footprint

      • Enables simultaneous and time-synchronous sampling, direct and straightforward

      MLE Mixed Signal FPGA

       

      Core Benefits of Mixed Signal FPGAs

      • Reduce your hardware footprint and parts count
      • No active peripheral ICs required
      • Efficient post-processing with low FPGA resource cost.
      • Highly reconfigurable analog-to-digital converter (ADC) / digital-to-analog converter (DAC) parameter setting
      • Design flexibility: „one more I/O“
      • Greatly reduce costs when applying multitudes of analog I/O channels
      • Reasonable I/O precision, more than sufficient for most of today’s analog applications in Embedded Systems
      • ADC sample rate: up to 200 kS/s
      • ADC resolution: up to 11 bits ENOB

      Applications

      • Flexible data acquisition and monitoring systems
      • Cost-efficient embedded systems with many sensor inputs
      • Voltage-based actuator control, DC motor control
      • Audio Output – that FPGA sounds great!
      • Integrated microcontrollers with reduced risk of parts obsolescence
      • Amplitude-Modulated (AM) protocol processing, for example IRIG

      Pricing

      MLE provides a suite of Intellectual Property (IP) Cores, reference designs, and design tools within a Mixed-Signal design suite. This complements the “soft” ADCs and DACs with optimized-for digital signal filtering and conditioning which takes the burdon of parametrization away from the user.

      MLE provides a three-phase product integration roadmap for new customers:

      Product Name Deliverables Example Pricing
      Requirements & Feasibility Analysis Integration service into customer project;
      • Option1: 1 parameterization, up to 6 channels; includes up to 5 engineering days
      • Option2: up to 3 parametrizations, up to 12 channels; includes up to 10 engineering days

      $6,650.-

      $13,300.-

      Production License IP license for one defined product; worldwide, fully paid up for, perpetual; up to 3 parametrizations, up to 33 channels per FPGA device family. Inquire

      Documentation

      Key-Value-Store Accelerator

      Data Center Acceleration

      Key-Value-Store (KVS) Accelerator 

      for Data Center Storage

      Data Center Acceleration with FPGA-based Storage Accelerator

      Xilinx, Fidus Systems and MLE have partnered to address the growing needs in High-Performance Computing and Data Center Acceleration to explore “unconventional” data-flow oriented FPGA-based system architecture for acceleration, hyperconvergence, object storage and in-memory compute.

      The outcome of this is ZU19SN – a high-capacity, hyperconverged, networked storage node with a Zynq UltraScale+ ZU19EG MPSoC.

      Featuring a network accelerator stack plus an out-of-order memory controller, high data throughput can be achieved while balancing between low-latency access and large storage capacities via integrated interfaces to connect to DDR3/DDR4 DRAM, Non-Volatile Memory Express (NVMe) Solid-State Disk (SSD), or SATA/SAS SSD or Harddisks (HDD).

      MLE is a licensee of Xilinx and offers sub-licensing, technology support and complementary design services for integrating KVS Accelerator technology into your application for Data Center Acceleration.

      Core Benefits

      • FPGA-based Key-Value load/store processing for data center server CPUs
      • “Full Accelerator” in programmable logic for line-rate TCP/IP and Memcached processing
      • Scalable performance to deliver processing speeds at 10, 25, 40, or 100 GigE line rates
      • Total Server Power reduction via heterogeneous computing architecture

      Applications

      • Accelerating Memcached servers in OLTP data center applications
      • Object storage for hyper-converged storage nodes
      • Hybrid SSD/HDD Key-Value Drives

      Key Features

      • Xilinx ZU19EP with dual NVMe m.2 SSDs and QSFP28 for dual 10/25/50/100 GigE
      • Quad-Core ARM A53 w/ Xilinx PetaLinux
      • Integrated System-on-Chip solution for Zynq Ultrascale+, or as PCIe-connected companion FPGA
      • Modular implementation in HDL and C/C++ for Vivado HLS. Supports Xilinx HLx and SDx design flows
      • Parameterizable for trade-offs between latency and capacity via DRAM, NVMe, SATA, SAS
      • Fully networked with 10/25/40/100 GigE connectivity
      • High-performance, low-power – many million responses per second (RPS) at over 200k RPS per Watt
        • 13M RPS at 35 Watts board-level, measured at 10 GigE
        • 100M RPS, extrapolated for 100 GigE
      • Tested and benchmarked on object sizes between 128 Bytes to 1M Bytes
      • Software-defined complete & customizable sub-system based on Xilinx IP cores for out-of-order memory controller, TCP/UDP/IP stack, hash table, DDR3/DDR4 DRAM, NVMe/SATA/SAS SSD and/or HDD interfaces

      Evaluation System

      Data Center Storage Accelerator Evaluation System - Zynq Ultrascale + MPSoC ZU19SN

      ZU19SN – a Zynq Ultrascale+ MPSoC 

      The ZU19SN Zynq UltraScale+ MPSoC Evaluation System is based on the Sidewinder-100 NVMe Storage Controller board from Fidus Systems:

      • Xilinx ZU19EP w/ quad ARM A53 and dual ARM R5
      • QSFP28 for dual 10/25/50/100 GigE
      • PCIe Gen3 x16 or Gen4 x8 system i/f
      • PCIe Gen3 x8 Host i/f
      • 2x PCIe Gen3/4 NVMe m.2 SSDs
      • 2x NGFF-8643 i/f for NVMe/SATA/SAS
      • 2x 16GB SoDIMM w/ ECC, PS- and PL-attached
      • Micro SD-Card, JTAG, UART, I2C, GPIO, …

      Pricing

      The KVS Accelerator for Data Center Acceleration is available as a combination of Intellectual Property (IP) Cores, reference designs, and design integration services:

      Product Name  Deliverables Example Pricing

      KVS Accelerator Device

      Integrated System-on-Chip solution, built on top of Xilinx Zynq-Ultrascale+ technology, integrating KVS acceleration with 10/25/100 GigE and SATA and/or NVMe, and others.

       Based on NRE and unit volume

      Inquire

       Intellectual Property (IP) Cores

      Single-Project or Multi-Project Use for Xilinx FPGA; Modular and application-specific IP cores, and example design projects; delivered as encrypted netlists or HDL/C/C++ source code. 

       starting at $115,000.-

      Inquire

      Application-specific R&D Services 

      Advanced KVS acceleration R&D services with access to acceleration experts from MLE, Xilinx or Fraunhofer HHI.   $1,480.- per
      engineering day

      Documentation

      Frequently Asked Questions

      ZU19SN is based on Xilinx Vivado 2016.4 and the matching Xilinx PetaLinux 2016.4.

      Yes, you can! However, we noticed minor glitches with u-boot in 2017.1 and plan to test 2017.2. Please keep in mind that both versions,Vivado and PetaLinux, must match. If not you may run into problems because the PL hooks (aka hardware) may be incompatible with the PS hooks (aka software), and again, may be incompatible with the HDF file. Therefore, Xilinx (and MLE) recommends to use identical versions for both! Zynq SSE is closer to the other hard IP core I/O functions inside the Zynq Processing System (PS), like UART or SDIO: It is fully instantiated and ‘frozen’ and cannot be altered – other than you are able to change the pin assignment.

      The Sidewinder-100 board from Fidus Systems is populated with an engineering sample ES2 of the Xilinx ZU19EG device. Please ensure that you have enabled beta device support. Please check back with our documentation on instruction for enabling beta device support.

      Yes, this project is all about collaboration. So, you will receive source code & scripts for the PetaLinux project plus for everything that is not a 3rd-party IP core.

      PCI Express (PCIe) Connectivity

      PCIe IP - PCI Express (PCIe) Connectivity​

      PCI Express (PCIe) Connectivity​

      ASIC / FPGA PCIe IP Solutions

      The Peripheral Component Interconnect Express (PCIe) standard currently in its sixth generation is an I/O interconnect technology defined by PCI-SIG. It is a layer based protocol that for software is fully backwards compatible to the PCI Local Bus standard which is replaced by PCIe.

      With the combination of cost-efficient high-speed serial IO and PCIe hard-IP blocks FPGAs can be connected to CPUs or GPUs or System-on-Chips (SoC) – or to other FPGAs to form a high-bandwidth, low-latency network in various topologies by using FPGA PCIe tunnels.

      To de-risk PCIe, MLE offers various hardware/software subsystems comprising open source Linux device drivers and pre-integrated FPGA reference designs, including PCIe SSD Host Controller, Linux PCIe Stream, PCIe Non-Transparent Bridging (PCIe NTB), and PCIe Long-Range Tunnel.

      PCIe SSD Host Controller

      MLE offers NVMe Streamer which is a so-called Full Accelerator NVMe host controller integrated into FPGAs. NVMe Streamer offloads the NVMe protocol into programmable logic and enables to stream data from FPGA blocks in and out of directly-attached NVMe SSDs. You can find more details on NVMe Streamer here .

      Linux PCIe Stream Framework for Xilinx

      PCIe as a hardware/software interface when combined with AXI4-Streaming suggests using a Streaming Dataflow architecture. This is also known as  Producer / Consumer or FIFO-In / FIFO-Out and uses so-called Blocking Reads and Blocking Writes for interfaces. Because AXI4-Streaming implements back-pressure / flow-control, a Blocking Read waits until there is data to be received, and a Blocking Write waits with sending more data in case FIFOs are full.

      Our FPGA PCIe Stream Framework for Xilinx FPGAs is a complete hardware/software subsystem comprising Linux device drivers (open source) and Xilinx PCIe function blocks, all delivered as a reference design (Xilinx Vivado project including all necessary TCL scripts, instantiating Xilinx catalogue IP, tested / synthesized on Xilinx Vivado and targeted to the Xilinx VCU118 Devkit).

      Our Linux FPGA PCIe Stream Framework supports the Xilinx PCIe hard-IP for Xilinx 7-series family, or newer.

      PCIe IP - Connectivity Framework

      PCIe Non-Transparent Bridging (PCIe NTB)

      PCIe NTB stands for PCI Express Non-Transparent Bridge. Unlike in a PCIe (transparent) Bridge where the RC “sees” all the PCIe busses all the way to all the Endpoints, an NTB forwards the PCIe traffic between the separate PCIe busses like a bridge. Each RC sees the NTB as an Endpoint device but does not see the other RC and devices on the other side. Means, everything behind the NTB is not directly visible to the particular RC, thus “Non-Transparent”.

      MLE’s patented PCIe NTB technology is provided as a complete hardware/software subsystem comprising Linux drivers for NTB with a network device API plus readily instantiated PCIe Endpoint plus an on-chip AXI4-Stream switching fabric.  It has been optimized for embedded applications such as automotive ECUs which typically are limited to maximum of 4 PCIe lanes. By borrowing performance techniques from NVM Express such as ring-buffers and posted-writes we can deliver a high-bandwidth, low-latency yet resource-efficient implementation.

      PCIe IP - PCIe Non-Transparent (PCIe NTB) Bridge Architecture

      The MLE Non Transparent Bridge supports the Xilinx PCIe hard-IP as well as soft-IP cores XpressRICH Controller IP for PCIe 3.1/3.0 (or newer) from PLDA or the Expresso Core from Northwest Logic / Rambus.

      FPGA / ASIC PCIe Long-Range Tunnel

      Based on a combination of network protocol acceleration technology from German Fraunhofer HHI and patented technology from MLE you can now extend the range of your PCIe connectivity well beyond the 12 inches supported by the standard and without the need to costly PCIe cables.

      PCIe IP - PCI Express over IP Architecture

      The fundamental concept behind is to transport PCIe Transaction Layer Packets (TLP) via TCP/IP, all implemented as a digital circuit in ASIC or FPGA. This guarantees reliable delivery and very deterministic delivery times. Optionally, this can be complemented by using real-time Ethernet such as AVB or TSN.

      Our PCIe Long-Range Tunnel subsystem supports the Xilinx PCIe hard-IP as well as soft-IP cores XpressRICH Controller IP for PCIe 3.1/3.0 (or newer) from PLDA or the Expresso Core from Northwest Logic / Rambus.

      Pricing of PCIe IP Cores

      Our PCIe Connectivity solutions are available as a combination of PCIe IP (Intellectual Property) Cores, reference designs, and design integration services:

      Product Name Deliverables Example Pricing
      Linux FPGA PCIe Stream Framework for Xilinx Single-Project or Multi-Project Use; Xilinx FPGA only; reference design project delivered as encrypted netlist or RTL.

      starting at $17,000.-

      Inquire

      NVMe Streamer Complete, downloadable NVMe Host and Full Accelerator subsystem integrated into the ERD example system. Delivered as Vivado design project with encrypted RTL code.

      starting at $24,800.-

      Inquire

      PCIe Non-Transparent Bridge (NTB) Single-Project or Multi-Project Use; ASIC or FPGA; Modular and application-specific IP cores, and example design projects; delivered as encrypted netlists or RTL.

      starting at $52,000.-

      Inquire

      PCIe Long-Range Tunnel Single-Project or Multi-Project Use; ASIC or FPGA; Modular and application-specific IP cores, and example design projects; delivered as encrypted netlists or RTL.

      starting at $66,000.-

      Inquire

      FPGA Application-specific R&D Services Expert PCIe R&D services for Intel or Xilinx FPGA. $1,480.- per
      engineering day

      Documentation

      Products Availability Matrix by FPGA Vendors

      Products Availability Matrix by FPGA Vendors

      MLE develops a close partnership with the key FPGA vendors and support a wide range of FPGA devices from AMD, Intel and Microchip for custom IP core design. The tables below high-light MLE Product Support as of April, 2023:

      Legend
      v Fully supported
      v Supported with restrictions
      v Supported, in development
      ! Support on Product Roadmap
        Not Applicable / no supported

      IP Core Availability for AMD Devices

      Supported AMD FPGAs for IP Core Design

      IP Core Availability for Intel FPGAs

      Supported Intel FPGAs for IP Core Design

      IP Core Availability for Microchip FPGAs

      Supported Microchip FPGAs for IP Core Design

      Looking for a specific FPGA for IP Core Design Service?

      Contact Us

        By submitting this form you are consenting to being contacted by the MLE via email and receiving marketing information.

        XAUI/RXAUI

        XAUI/RXAUI IP Cores

        XAUI/RXAUI

        AMD/Xilinx Legacy IP Cores for XAUI/RXAUI

        The Xilinx XAUI/DXAUI IP Core and the Xilinx RXAUI IP Core used to be part of the Xilinx Vivado tool chain until 2019.1 and was available Xilinx End User License Agreement. As of May 2020, Xilinx handed over support and distribution of the XAUI/RXAUI IP Cores to MLE. MLE has been supporting customer projects with these IP Cores and will continue to provide to Xilinx users long term support.

        We are able to include the Questa/Mentor public key into our encrypted IP-Cores, which allows us to integrate the IPs via Vivado or simulate the IPs in Questa (requires IEEE1735 V2 encryption). Depending on customer needs, we generate encrypted netlists or encrypted source code.

        XAUI/RXAUI IP Cores - Block Diagram

        XAUI IP Cores

        The Xilinx XAUI (eXtended Attachment Unit Interface) IP Core is a high-performance, low-pin count 10-Gb/s interface intended to allow physical separation between the data link layer and physical layer devices in a 10-Gigabit Ethernet system.

        The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the UltraScaleTM architecture  (GTHE3 transceivers), Zynq®-7000 All Programmable SoC, and 7-series devices.

         
        Architecture of XAUI IP Core

        RXAUI IP Cores

        The Xilinx LogiCORE IP RXAUI core is a high-performance, low pin count 10 Gb/s interface intended to allow physical separation between the data-link layer and physical layer devices in a 10 Gb/s Ethernet system.

        The RXAUI core implements a single-speed full-duplex 10 Gb/s Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx® 7 series FPGAs and UltraScale architecture (GTHE3 transceivers) that comply with Dune Networks specifications. The 7 series FPGA and UltraScale architecture in combination with the RXAUI core, enable the design of RXAUI-based interconnects whether they are chip-to-chip, over backplanes, or connected to 10 Gb/s optical modules.

        Implementation of Dune Networks of RXAUI IP Core

        Pricing

        The XAUI/RXAUI IP Cores are available as Intellectual Property (IP) Cores and design integration services:

        Product Name Deliverables Pricing

        XAUI IP Core

        Single-Project-Use; delivered as encrypted netlist.

        $14,500.-

        RXAUI IP Core

        Single-Project-Use; delivered as encrypted netlist.

        $14,500.-

        XAUI IP Core Multi-Project-Use; delivered as encrypted netlist. $21,800.-
        RXAUI IP Core Multi-Project-Use; delivered as encrypted netlist. $21,800.-
        XAUI and RXAUI IP Core Bundle Single-Project-Use; delivered as encrypted netlist. $21,800.-
        XAUI and RXAUI IP Core Bundle Multi-Project-Use; delivered as encrypted netlist. $28,800.-

        Application-specific R&D Services

        Network protocol expert design services.

        $1,480.- per engineering day  

        Documentation