Resources - Missing Link Electronics

Enabling PTP-based Time-of-Day Synchronization via 5G Sidelink

July 11, 20255G Sidelink, 6G, GNSS, Precision Time Protocol (PTP), Real-Time, Time Synchronization

Presentation at 6G Conference 2025, Berlin, Germany, July 3rd, 2025

MLE Enabling PTP-based Time-of-Day Synchronization via 5G Sidelink

GNSS is widely used for positioning and synchronization—particularly in applications, such as vehicles and drones, where merging recorded radar data and coordinating multiple nodes over-the-air is essential. Accurate time-stamping is crucial to ensure data integrity, which requires a reliable and common time source. However, GNSS connectivity can be limited or completely unavailable in challenging environments like tunnels or urban canyons, making precise synchronization difficult.

In this presentation, MLE showcases our approach to synchronize devices using PTP-based application layer time synchronization over 5G sidelink. We walk through the approach and implications of correlating PTP messages with 5G PHY layer frame timing, and briefly touch on a method for further improving the timestamp accuracy. In the end, we present our proof-of-concept demonstrator setup developed in collaboration with Fraunhofer HHI, along with initial experimental results, demonstrating microsecond-level time synchronization accuracy via PTP over 5G sidelink. Notably, this approach relies purely on existing mechanisms and requires no additional modifications to future 6G standards.

To learn more about the details, download the slides below or contact us for more information.

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White Rabbit at MLE – Updates on Dormouse FMC Card, Light Rabbit and Further Contributions

July 10, 20256G, AMD ZC706, AMD ZCU102, Dormouse FMC, GNSS, Precision Time Protocol (PTP), Radar, Time Synchronization, White Rabbit

Presentation at the 14th White Rabbit Workshop 2025 at CERN in Geneva, Switzerland, Jun 25-26, 2025

White Rabbit at MLE - Updates on Dormouse FMC Card, Light Rabbit and Further Contributions

White Rabbit is a technology that allows to synchronize networked devices or endpoints tens of kilometers apart with a sub-nanosecond accuracy. It is now fully integrated into the IEEE1588-2019 or PTP v2.1 standard as high accuracy (HA) profile. Each endpoint employs frequency and phase measurement and adjustment techniques using field programmable gate arrays (FPGAs) and external voltage-controlled crystal oscillators (VCXOs). However, this usually requires external circuit boards with specific components, which is not available on commercially off-the-shelf (COTS) development boards.

This talk provides an overview about the most major steps on White Rabbit within MLE. We present our journey with the Dormouse FMC, featuring tunable oscillators that are required to deploy and operate White Rabbit, and the enablement of it for AMD ZCU102, ZCU106, ZCU111 platforms. Based on this development a bistatic RADAR setup has been built together with and at KIT. The respective setup is also used in 6G massive MIMO experiments.

As a side effect of the Dormouse related developments some basic FMC Card support, SiT3521 operation, extensions to the HMC7044 CLI command, GTY transceiver support, etc. have been added, which currently wait for MRs to be opened.

In parallel a ZC706 and X310 based White Rabbit implementation has been put together using the PICXO approach, which is used in one of the research projects. The same project received refined GNSS support, which is publicly available as an MR already.

To enhance the accuracy of the AMD devkit based MLE WR nodes an initial absolute calibration session has been carried out together and at KIT.

We also provide a peek into our test infrastructure and an outlook into what we plan to achieve throughout the rest of this year.

To learn more about the details, download the slides below or contact us for more information.

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FPGA-Based Highly Configurable and Low-Latency Multi GMSL Camera 10GbE RTP Streaming: Performance and Design Choices

July 7, 2025Analog Devices, High Speed Camera, Low Latency, Precision Time Protocol (PTP), Real-Time, TCP/UDP/IP

Presentation at FPGA Conference 2025, Munich, Germany, July 3rd, 2025

MLE FPGA-Based Highly Configurable and Low-Latency Multi GMSL Camera 10GbE RTP Streaming: Performance and Design Choices

In the decade of high-performance networking and computing, FPGAs have arisen as a promising and highly convenient solution, offering flexibility, reprogramming capacity and parallelism options. The role of high-performance solutions that offer a high throughput in network-related operations is extremely beneficial in real-time processing tasks executed on embedded systems, such as real-time video streaming.

In this presentation, MLE and Analog Devices showcase the capabilities and obtained performance of our FPGA-based high-speed multi GMSL camera to RTP streaming solution using a single 10GbE link. There will be a walk through the multi GMSL Ser/Des integration, and the FPGA-powered components overview: the CSI-2 to RTP streams translation and the multi-GMSL camera synchronization, accompanied by the highly configurable and low-latency UDP/IP network accelerator. The described high-performance data path is integrated with the on-chip CPU subsystem to provide time synchronization via PTPv2 and enable control and monitoring of the device via the network. At the end of the presentation, we emphasize the most important design choices to build such a multi-camera streaming system. We finally draw the conclusions and the lessons learned from that successful experience.

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Looking for TCP/UDP/IP Accelerator for Image/Video Streaming?

Visit MLE Network Protocol Accelerator Platform (NPAP)

In-Vehicle Network – Automotive Zone-based Architecture with Time Sensitive Network – Auto/TSN

July 7, 2025Auto/RPS, auto/tsn, Automotive, CeCaS, Time-Sensitive Networking (TSN), Zonal Architecture, Zonal ECU

Presentation at FPGA Conference 2025, Munich, Germany, July 3rd, 2025

MLE In-Vehicle Network – Automotive Zone-based Architecture with Time Sensitive Network

Automotive architectures are transforming: while more and more sensors become integrated in vehicles, the automotive industry is looking for ways to reduce wiring efforts in production, more scalability, higher level of integration and faster ways development.

Auto/TSN stands for automotive data over Time-Sensitive Networks which is an in-vehicle network infrastructure based on open standards such as IEEE Ethernet.

Auto/TSN virtualizes the in-vehicle network infrastructure: Key objective is to reduce costs, increase scalability and enable upgradability for next-generation automotive architectures including electric and/or autonomous vehicles.

The presentation will show how a zone based architecture can look like in comparison to the “classic” wiring. It will explain the tasks of a zone gateway and why FPGA/SoC play a major role in sensor fusion. Further more why it is important to use middleware which turns devices in a service for a central car server and other ECUs. For visualization, we will show examples of the government funded CeCaS research project and show the complete chain from camera sensors over zone gateways to the central car server.

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Looking for Automotive Rapid Prototyping System (Auto/RPS) for Zonal ECU?

Learn More About MLE Auto/RPS

Zonal/SDV Architecture Exploration: From Whiteboard to Vehicle Demo in 9 Months

June 17, 2025ADAS, Auto/RPS, auto/tsn, Fast FPGA RAID, FFRAID, trenz, Zonal Architecture

Presentation at AMD Technology Day, Gothenburg, Sweden, June 4th, 2025

Zonal Architecture powered by MLE AutoRPS

For the AMD Technology Day in Gothenburg, Sweden, MLE presented an automotive rapid prototyping system for architecture exploration and development of future Zone based automotive architectures. The outcome presented based on a practical example of work done in the MANNHEIM CeCaS Project. The CeCaS Project is funded by German Federal Ministry of Research, Technology and Space (BMFTR) initiative MANNHEIM and focuses on central car server architectures and super computing platforms for autonomous vehicles.

Driven by the needs, and constraints, of the CeCaS Project MLE and partner Trenz Electronic have put together an Automotive Rapid Prototyping System (Auto/RPS) based on AMD’s Versal Edge AI devices.

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Complementing TCP with Homa, Stanford’s Reliable, Rapid Request-Response Protocol

October 8, 2024Homa, Network Acceleration, SmartNIC, TCP/IP

Presentation at SNIA Storage Developers Conference, Santa Clara, CA, Sept. 16-18, 2024

At SDC 2023 last year, we presented Homa, a new datacenter protocol invented by John Ousterhout at Stanford University. Overall, Homa provides significant advantages over TCP when it comes to tail latency and infrastructure efficiency in real-life networks, but not compatible with TCP API. We were told to come back with answers regarding Homa:

A) Can Homa and TCP co-exist in the same network peacefully?

B) How can Homa be accelerated to become more useful and applicable for networked storage?

In our presentation this year we will provide those answers and new collaboration results.

First, we will show network simulation analysis for traffic comprising Homa and TCP. Because of TCP’s congestion management, both protocols not only can co-exist but also be complemented in order to get the best from both: TCP for data streams plus Homa for (shorter) messages with improved tail-end latencies.

We then look into John’s open source implementation for the Linux Kernel, HomaModule and how this can be combined with another open source project, FPGA NIC Corundum.io, for FPGA acceleration of the Homa protocol.

We present experimental results by applying known concepts of CPU offloading to Homa, especially receive side scaling (RSS), segmentation and large receive offloading. After applying the offloads to a traffic pattern with significant traffic portion of payload chunks, the MTU (maximum transmission unit), both the slowdown and RTT, decreases by 5x. The outcome is a Reliable, Rapid, Request-Response Protocol with benefits in storage networking and potential use for networking GPU clusters.

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FPGA Based 400GBit/s Data Recorder – Insight into Different Pitfalls and Design Choices

July 8, 2024BRAM, High Bandwidth Memory (HBM2), High Speed Data Recording, NVMe SSD, PCI Express, Storage Acceleration

Presentation at the FPGA Conference 2024, Munich, Germany, July 2, 2024

MLE - FPGA Based 400GBit_s Data Recorder - Insight into different pitfalls and design choices

Modern Systems can combine a lot of sensors like cameras, radars, Lidar or high speed ADC/DAC. During development, it is often required to record raw data. A FPGA Based High Speed Recorder can collect data from many different sources and can record them on non-volatile memory. Building a High Speed Data Recorder has many pitfalls which can cause the project to fail as a single flaw can have a heavy impact on performance.

This presentation will walk through our lessons learned from building such a recorder: starting by analyzing the data path, discussing the impact of data granularity and data width, different local buffer options such as DDR / HBM2 / UltraRAM / BRAM, characteristics of AXI4 / PCIe and also the limitations of most NVMe SSDs in the aspect of sustained writing performance. Then the presentation will end with an architectural overview of the final system and the achieved performance.

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Architecture and Performance of Integrated High-speed and Versatile Embedded Networking

April 17, 2024AMD, High Speed Data Streaming, Network Acceleration, Precision Time Protocol (PTP), SmartNIC, ZYNQ Ultrascale+

Presentation at the Embedded World 2024, Nuremberg, Germany, Apr. 11, 2024

These days high-performance embedded systems operate highly interconnected. Within these networks the systems often transport data at high bandwidth or low-latency. While the system needs to serve the network performance needs, additional control tasks are to be performed. For the latter task usually a processing system runs a Linux or another real-time embedded operating system. Then the former, high-performance network data cannot be fully handled by the embedded processing system. Thus a high-speed and Versatile Embedded Networking is needed.

To overcome this situation, a network stack implemented in hardware, e.g. in an FPGA, can offload the processing subsystem. To simplify the system design and reduce cost, the number of physical networking interfaces can be reduced to one. This, on the other hand, requires an architecture that shares a single high-speed network interface across the processing system and the hardware network stack. Usually, embedded systems in addition require highly accurate time synchronization, usually provided via PTPv2.

The presentation shares the architecture options and results based on an implementation for a high-speed streaming data interface, both a source and a sink that shares a physical network interface with a open source network interface card implementation connected to a processing system. This NIC is operated by a Linux driver and allows for PTPv2 based time synchronization via a Linux daemon. The whole system is implemented into an AMD MPSoC.

To learn more about the details, download the slides below or contact us for more information.

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TCP/IP for Real-Time Embedded Systems: The Good, the Bad and the Ugly

April 17, 20246G, auto/tsn, FPGA, Homa, Homa Protocol, Network Acceleration, NPAP, NVMe, Robo/TSN, TCP/IP

Presentation at the Embedded World 2024, Nuremberg, Germany, Apr. 9, 2024

TCP/IP stream scheduling for Real-Time Embedded Systems

Embedded systems such as in-vehicle networks, modern factory automation or autonomous robots, for example, are undergoing a major shift: Enabled by high-resolution cameras, Radar and Lidar sensors, AI algorithms can implement smartness and ambient awareness, but this need more compute power and higher bandwidth. Industrial and automotive networks must now transport many Gigabits per second, while guaranteeing reliable and secure data delivery, on-time. Thus real-time embedded systems are needed.

TCP, the Transmission Control Protocol, was introduced half a century ago and is a good protocol used almost everywhere in wired or wireless, robotics, factories, vehicles. Unfortunately, TCP has some bad aspects: A significant computational burden. And some outright ugly: Unpredictable tail latency and head-of-line blocking, making real-time behavior difficult.

Our presentation shares quantitative analysis results and presents alternatives: For latency analysis we present benchmarks results from network simulation which show the significant tail latencies for TCP and the undesirable outcomes of TCP’s “not-so-fair” scheduling.

As an alternative we present the Homa protocol from Stanford University. Instead of stream-based connections, Homa is message based and connectionless, which caters better to the needs of modern distributed, microserviced, virtualized embedded architectures. Homa provides significant advantages over TCP when it comes to tail latency and infrastructure efficiency in real-life networks.

To learn more about the details, download the slides below or contact us for more information.

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